1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices and integrated circuits, and more particularly to a structure and method for fabricating a self-aligned, sub-minimum guard ring for a Schottky Diode.
2. Description of Related Art
Schottky diodes are prone to high electric field regions at the corner of the ion implant regions where the metal or silicide of the diode structure meets the isolation structure. Typically, this electric field prohibits the diode from performing at its optimum characteristic level. Parameters that are adversely affected by this field include the reverse bias leakage current and breakdown voltage.
The use of a Schottky diode generally allows integrated circuits to have greater speed because it is a majority carrier device. Having a low carrier lifetime attributes to its greater switching speeds. Additionally, this type of diode requires a smaller voltage signal for switching. A typical application of a Schottky diode is as an anti-saturation diode clamp.
Current approaches at eliminating the high electric field regions near the isolation barriers consist of adding a guard ring at the edge of the isolation structure. In the case of an n-type Schottky, the guard rings are added at the n-regions around the Schottky contact region. This provides for a better diode; however, it results in parasitic capacitance and slower device operation. It also enlarges the device considerably due to the need for a second mask and the tolerances associated with additional processing.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to fabricate an improved low-leakage Schottky diode with a guard ring that minimizes the electric field and leakage current generated at the perimeter of the deposited metal or silicide layer that forms the Schottky contact.
It is another object of this invention to provide a method that minimizes the size of the guard ring thereby enhancing the device cell density and reducing the parasitic capacitance.
It is a further object of this invention to eliminate the need for an additional mask in the fabrication of the guard rings thereby reducing the associated stack up of tolerance errors in the fabrication process.
It is yet another object of this invention to deposit ion implant regions within the substrate at a depth level near the top and bottom of the isolation structures to tailor the surface of the diode and reduce the series resistance.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.